A fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform

This paper presents a fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform. By utilizing the guard interval in OFDM signals, the coarse symbol synchronization (CSS) and the fractional carrier frequency offset estimation (CFO) are considered simultaneously. The multi-core processor platform is a 2-Dimension mesh array of SIMD (Single Instruction Multiple Data) cores, and is well suited for digital communication applications. By exploring the task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access, and route-length-minimized task mapping techniques, the implementation can achieve a throughput up to 224Mbps, which shows the great advantage of multi-core processor platform.