Through-silicon via (TSV) capacitance modeling for 3D NoC energy consumption estimation

Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail, and by comparing against Monte Carlo simulations in Silvaco. About 6.9% and 10.1% error of mathematic model exists to simulation results and measurement results. By integrating the model in NoC simulator, the energy consumption of network can be estimated quickly and accurately.