A 8.5 GHz phase locked loop with split-load divider

This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 µm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes around 5mW power with 1.2V supply. The 8448 MHz PLL achieves phase noise of −92 dBc/Hz at frequency offsets of 100 kHz and has a reference spur of -56 dB with the second order passive low pass filter. The whole circuit (without test buffer) consumes only 13mA for a 1.2V power supply with die area of 0.9×1.3mm².