A novel vector/SIMD multiply-accumulate unit based on reconfigurable booth array

This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes are obtained by combining these elements selectively. This MAC unit can also perform multiply between scalar and vector operands. 32-bit SIMD (Single Instruction Multiple Date) extended ISA (Instruction Set Architecture) and 3-stage pipeline are implemented for the MAC unit. The design is synthesized in 0.13um SMIC technology under worst case condition, and the critical path of MAC is 2.5ns.