Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors

This paper presents fast architectures for the forward and inverse transforms of the H.264/AVC video compression standard. These transforms can be computed exactly as in integer arithmetic, thus avoiding mismatch problems between the encoder and decoder. They are inserted into the T and T
^-1
block of the H.264/AVC and they can be computed by using only additions and shifts. Since the transforms algorithms are composed by a large number of addition/subtraction, fast architectures for the 4×4 Discrete Cosine transforms and 4×4 and 2×2 Hadamard transforms are proposed using efficient hierarchical adder compressors. The designs were described in VHDL and mapped to TSMC 0.18μm CMOS standard cells. Experimental results show that the architectures using 8-2 adder compressor can reach high frequency operation, high throughput and they are more efficient than the solutions of the literature.