Accurate estimation of on-chip global RLC interconnect delay for step input

In this paper, firstly, we have calculated the delay through an ideal RLC transmission line model, without the driver and the load impedance. This yield's to the transform voltage and current equations governing the system response by incorporating appropriate boundary conditions for interconnect delay analysis. Two port parameters in terms of ABCD matrix are obtained. Further we considered a practical transmission line with driver and load to find the relation between the transform input and output voltage response in s-domain. The relation thus obtained is applied to step input system and the transient response for it in time domain is obtained using inverse Laplace transform. Our main objective is to find the shape function of a wire which minimizes delay for RLC circuit. Although the problem has been studied under the Elmore delay model, it is only a rough estimate of the actual delay and more accurate estimation of the actual delay should be used to determine the wire shape function. The use of transmission line model in our study gives a very accurate estimate of the actual delay. Previous studies under Elmore delay model suggest that exponential wire shape function to be of the form f(x)=ae^−bx. By solving the diffusion equation, we derive the transient response in the time domain as a function of a and b for step input. The coefficients a and b are determined so that the actual (50% delay) is minimized.