FPGA-based high resolution synchronous digital pulse width modulator

Advantages of digital control in power electronics have led to an increasing use of digital pulse width modulators (DPWM). However, the clock frequency requirements may exceed reasonable limits when the power converter switching frequency is increased while using classical DPWM architectures. This paper presents a novel synchronous design to increase the resolution of DPWM implemented on Field Programmable Gate Arrays (FPGA). The proposed circuit utilizes the Phase Shift (PS) functional unit of the on-chip Digital Clock Manager (DCM) blocks available on modern FPGAs, operating in fixed mode. This solution has been implemented, tested and compared to other implementations.