Practice on layout-level radiation hardened technologies for I/O cells

Radiation hardened technologies are important to improve the anti-radiation performance of ICs. In this paper, several I/O cells in 0.18μm CMOS process are designed and radiation hardening technologies through layout design are researched. The function, timing and the effect of the ESD protection scheme for the I/O cells are analyzed by HSPICE simulation. The way of layout-level radiation hardening consists of single event effect and total ionizing dose effect. TCAD simulation is used to analyze the validity of the technologies adopted in the paper, and the experimental results indicate that the single event latch-up threshold increases effectively, and the anti-radiation performance is improved.