Power Integrity Analysis for High-Speed PCB

In high-speed digital circuit, supplying a clear power to the integrated circuit and managing the coupling of power noise which can cause fluctuations or disturbances in the power distribution system have become the bottleneck of high-speed digital circuit designs. So it is expected to be a challenging problem for the power integrity (PI) design due to the wider bandwidth of the noise. Keeping the power distribution network (PDN) impedance very low in a wide frequency range and reduce simultaneous switching noise (SSN) are priority ways for the power integrity (PI) design. The decoupling capacitors are conventionally used to minimize the power impedance at a frequency where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. This paper investigates both in time and frequency domains the power integrity with the help of full-wave finite-element simulations. The solution which is based on the decoupling capacitors is reviewed in this paper. Besides, the placement and value of the decoupling capacitors will be discussed.