Design space exploration and optimisation for NoC-based timing sensitive systems

Communication modelling and synthesis plays an important role in the design of complex network-on-chip (NoC) based timing-sensitive systems-on-chip (SoC). To guarantee timing constraints without detailed know-how of communication might lead to unexpected results. In our previous work we have proposed an approach for communication modelling and synthesis to calculate communication hard deadlines that are represented by communication delay and guide the scheduling process to take into account possible network conflicts. In this paper we combine our communication scheduling approach with global optimisation techniques to perform design space exploration and/or improvement of the synthesised schedule.