Design of 16-channel CAGO-CFAR ASIC block with target-eliminating circuit

In this paper, a kind of circuit with the logarithm cell-averaging greatest-of selection (GO-CFAR) eliminating estimate cell target is introduced, which can make 16 channels CFAR processing in 4.8 /spl mu/S. The main characteristics of the circuit which is single ASIC chip is designed with standard cells, and can eliminate the effect of big targets upon the estimate level. The chip consists of clock generator, arithmetic section and internal RAM with 11 K BIT, totally 13000 gates.