P-type complementary pass-transistor adiabatic logic circuits for active leakage reduction

With rapid technology scaling, gate leakage has become a significant component in currently used nanometer CMOS processes without high-k metal gate structure. This paper presents a P-type implementation scheme for complementary pass-transistor adiabatic logic circuit (P-type CP AL) to reduce the gate-leakage power dissipations, which consist mostly of PMOS transistors. A full adder is verified using the P-type CP AL scheme. All circuits are verified with HSPICE using the 65nm CMOS process with gate oxide materials. BSIM4 model is adopted to reflect the characteristics of the leakage currents. Based on the power dissipation models of CP AL adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. Compared with traditional N-type CP AL counterparts, the proposed P-type CP AL circuits consume low static power, because PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones.