Multi core implementation of a trellis based syndrome decoder with adaptive complexity

This paper investigates the implementation of a trellis based syndrome decoder on symmetric multiprocessor (SMP) platforms. Two advantages of the proposed approach will be exposed: First, compared to conventional parallel Viterbi decoder implementations, the syndrome decoder achieves a higher parallel efficiency in terms of speedup on the SMP platform. This is realized by reducing the computational overhead of the parallel Viterbi algorithm implementation. Second, it offers an adaptive complexity, i.e. the number of decoding operations decreases with improving transmission conditions. This property can be exploited to reduce the average energy consumption of a radio receiver. Measurement results are shown for two SMP platforms: ARM's MPCore and Intel's Core i7.