On-chip ESD protection with improved high holding current SCR (HHISCR) achieving IEC 8kV contact system level

For the design of on-chip ESD clamps against system level ESD stress three main challenges exist: reach a high failure current, ensure latch-up immunity and limit transient overshoots. Bearing these in mind, high system level ESD requirements should be within reach. A novel improved high holding current SCR is introduced fulfilling all three requirements within drastically reduced silicon area.