A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three decades. Implemented in 0.13 μm CMOS, the circuit occupies 0.06 mm², while its power dissipation is 9 pW/Hz, proportional to the output clock frequency with 350 nW stand-by power. The circuit remains stable with scalable dynamics for frequency steps (upward and downward) as large as a factor of ×1024. The presented clock generator has been designed to be compatible with subthreshold source-coupled logic (STSCL) topology that can be used for ultra-low power applications such as in bio-medical systems.