A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application

An outphasing power amplifier (PA) is designed and implemented in a 32nm digital CMOS process. The PA uses a transformer power combining configuration with reduced losses at backoff power. In the range of 2.2-2.5GHz, this PA gives 25dBm peak CW power with 40% total efficiency (includes all drivers). The class-D PA takes advantage of 32nm switching speed to achieve good linearity performance. The PA delivers 18dBm average power with 18% total efficiency while meeting 64-QAM WLAN requirements, with no need for linearization.