Repetitive avalanche cycling of low-voltage power trench n-MOSFETs

Low voltage discrete power trench n-MOSFETs in TO-220 packages have been subjected to over 200 million cycles of repetitive unclamped inductive switching (UIS) at a mounting base temperature of 150° C and at different avalanche currents. Hot-hole injection into the gate dielectric during avalanche conduction causes a reduction in the threshold voltage as the number of avalanche cycles increase. The relationship between the change in the threshold voltage and the number of avalanche cycles is shown to be a power-law with the pre-factor dependent on the test conditions and the MOSFET technology. Experiments show that the power law pre-factor is proportional to the avalanche current in agreement with the predictions of the “lucky-electron” model. Interestingly, the pre-factor also responds proportionally to the MOSFETs cell pitch. A 40% increase in the avalanche current caused a 30% increase in the power law pre-factor while a 37.5% reduction in the MOSFETs cell pitch caused a 40% reduction in the power law pre-factor. Smaller cell pitch MOSFETs also exhibit improved on-state resistance stability with avalanche cycling however with higher drain-source leakage.