Parallelized cyclostationary feature detection on a software defined radio processor

The accurate and timely spectrum sensing ability is very critical to cognitive radio. Cyclostationary feature detection has the ability to separate the signal of interest from noise and/or interference, but the computational complexity of cyclic spectral analysis limits its use as a signal analysis tool. To reduce the computational complexity of cyclic spectral analysis, this paper proposes an efficient parallel FFT accumulation method (FAM) algorithm and realizes it on a novel SDR processor for next generation wireless communication, GAEA. The simulation results show the parallel FAM algorithm's processing time on an 8 MHz BW signal at frequency resolution of 512 Hz requires approximately 78.8 ms. This approach will be suitable for spectrum sensing of cognitive radio and other cyclostationary feature detection applications.