A comparative 3D simulation approach with extensive experimental Vt/Avt data and analysis of LER/RDF/reliability of CMOS SRAMs at 40-nm node and beyond

With the advent of CMOS SRAMs manufactured at 40-nm node and beyond, variability of threshold voltage (Vt) and technology-dependent factor in Pelgrom plot (Avt) has become a serious issue in the practical design and fabrication phases. This paper presents (i) a comparative 3D simulation approach using extensive measured data to clarify the magnitudes of LER and RDF effects in generic processes, (ii) estimation of magnitudes of LER, RDF and FER (metallurgical junction front edge roughness) effects, (iii) simulation of LER, RDF and FER in a FinFET device to evaluate practical feasibility and (iv) analysis of size-dependent NBTI-induced Vt fluctuation as a possible application of this method.