Physical implementation of a baseband MC-CDMA downlink receiver

A baseband multi-carrier code division multiple access (MC-CDMA) downlink receiver meeting wideband CDMA (WCDMA) bandwidth requirements is simulated and implemented into a field programmable gate array (FPGA) platform. The receiver was designed and implemented to achieve low FPGA resource consumption via the use of low-complexity DSP algorithms and temporal multiplexing techniques. Bit-error-rate (BER) measurements were performed using a laboratory static wireless channel setup in the 2.4 GHz unlicensed band with different modulation schemes and numbers of active users. Measurement results show good agreement with system simulations.