Detecting delay flaws by very-low-voltage testing

The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage-between 2 and 2.5 times the threshold voltage V/sub t/ of the transistors. A delay flaw is a defect that causes a local timing failure but the failure is not severe enough to cause malfunctioning. Delay flaws caused by degraded signals and gates with lower drive capability than expected are considered. This paper investigates the voltage dependence of the effects of delay flaws and derives the test conditions for them.