Π-gate nanowires TANOS poly-Si TFT nonvolatile memory

This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (II-gate) structure. II-gate structure in this TANOS NVM increase on current (I_on), decrease threshold voltage (V_th) and subthreshold slope (SS), and enlarge the memory window (ΔV_th). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 μs. The 70 % of initial memory window has been maintained after 10⁴ P/E-cycle stress.