Data acquisition algorithm of logic-unknown synchronization sequential machines

With the rapid development of VLSI (very large scale integrated circuits), programmable logic devices have made great progress in integration level, manufacturing technology and encapsulation technique, which make its functions more complex and the reverse analysis of it becomes more difficult. As an important component of the reverse analysis of the logic-unknown chip, the processing capacity and efficiency of data acquisition subsystem has a direct effect on the whole analysis system. Consequently, how to acquire the complete and accurate data set rapidly under limited space and time restricted condition has become the most difficult problem in the design of data acquisition. In this paper, the key problem state drive is raised. The feasibility that implements state drive of logic-unknown synchronization sequential machines by establishing full state transition diagram is proved. Furthermore, the existing algorithms for data acquisition are introduced and the performances of which are given. At the end of the survey, some vital problems of state transition diagram are presented and analyzed.