Electrical characteristics of silicon nanowire transistor fabricated by AFM lithography

Atomic force microscope (AFM) nanolithography was performed to create nanowire transistor pattern via local anodic oxidation process on surface of silicon-on-insulator (SOI) wafer. This nanoscale oxide pattern is used as a mask system for chemical etching to produce silicon nanowire transistor. The device with component structures of a silicon nanowire as channel with source, drain and gate pads had been drawn. The designed device was etched with TMAH to remove uncovered silicon layer and HF to remove oxide layer. From the AFM and FESEM observation found that the SiNWT with wire size of 92.65 nm in wire thickness, 90.83 nm wire width, and 10.30 μm in length and 175.17 nm distance wire-gate with contact pads size of about 5 μm × 5 μm has been successfully fabricated. The I-V characteristics indicated that the drain current was affected by the applied gate voltage similar to p-type FET.