A 125-ps access, 4GHZ, 16Kb BiCMOS SRAM

A 128Kbit BiCMOS SRAM with a typical access time of 125ps was developed with 0.13um IBM Silicon Germanium BiCMOS technology. The fast access time with moderate power dissipation has been achieved using following techniques: CML decoder, CML driver circuit, bipolar sense amplify. CMOS 6T memory cell is used to achieve the high packing density. The simulation demonstrates that this SRAM macro can achieve working frequency of 4GHZ. This Macro is especially useful for realizing ultrahigh speed, high density SRAMs which is used as cache in the super computing processor.