A method for efficient implementation of reliable processors

Reliability is becoming an important feature of digital circuits implemented on deep submicron technologies. Fault tolerance techniques can be used in order to improve the circuit's reliability but leading to some kind of design penalties (area, time, power consumption). In this work, we propose a method that takes into account reliability and other classic design parameters when choosing the most suitable architecture. In addition, the designer is free to establish different cost-performance tradeoffs according to the target application.