Dynamic Programming Addition Optimization approach for large size multipliers in FPGAs

In this paper, Dynamic Programming Addition Optimization (DPAO) approach is proposed to realize large size multipliers targeting FPGA devices. The large size operands of the multipliers are decomposed and multiplied to generate segmented partial products. Each segmented operation is processed by embedded blocks in FPGAs, and then multi-level addition is performed to obtain the final result. The objective of the DPAO technique is to achieve highly optimized addition with delay-area as a cost function. The implementation results are compared to Standard approach and to Karatsuba-Ofman multipliers targeting Xilinx' and Altera's FPGAs. When using Altera's FPGAs, the average improvement in speed is 5.3% and LUT savings is 28.8% for operands ranging from 40 bits to 112 bits. Improvements in Xilinx implementation are limited to operand sizes of more than 70 bits.