A medium-grain reconfigurable processing unit

In this paper the components required to implement a central processing unit (CPU) and its arithmetic logic unit (ALU) are presented using a novel medium grain reconfigurable hardware architecture. The CPU can be configured to match the application's requirements in terms of word-size, number and type of units, and instruction set. The MIPS instruction set has been used to show the potential of the processing unit. The clock for this implementation is calculated to be in the order of 2GHz for current technologies.