Multi-chip architecture for IF Neural Network

The design of a multi-chip architecture can be an appealing solution to implement very large Artificial Neural Networks systems. The size of these systems often can be a only way to deeply and effectively investigate on innovative, “bioinspired”, computational paradigms. In this paper, the authors present the architecture of a system with two analogue chips well suited to carry out a large Integrate and Fire Neural Network electronic system. In particular, the chips have been designed by using a dedicated technique to reduce the I/O analogue pins.