Design aware scheduling of dynamic testbench controlled design element accesses in FPGA-based HW/SW co-simulation systems for fast functional verification

In HW/SW co-simulation based logic verification systems [1, 2], the design under test (DUT) is executed on an FPGA based emulator and the behavioral testbench written in some high level language like C or HDL is run on a SW simulator or a general purpose CPU. In such systems it is essential to reduce the communication between SW and HW sides to enhance overall verification speed. Therefore it is of significant importance to efficiently schedule testbench controlled accesses to design elements like flip-flops, memories etc, which require access to FPGA HW. Such accesses by static HDL testbenches which are specified at design compilation time and are mainly to design IOs are optimized by synthesis of RTL transactors [6, 7, 8, 9], which make use of specialized high speed links and standardized interfaces like SCE-MI [13] for optimizing the transactions. It is seen that apart from static testbenches, verification engineers and designers often make use of dynamic random access to design elements (e.g a series of register sets) through C or TCL based dynamic testbenches typically specified post design compilation. Such dynamic accesses are not routed through the transaction link and follow a fixed cost scheduling, resulting in sub-optimal communication pattern between SW and HW verification engines. The paper presents a design aware scheduling system for optimizing such dynamic accesses, by extracting and making use of design characteristics for intelligently clubbing and scheduling various read/write accesses while maintaining modeling fidelity. This complements the streaming transaction based interfaces available for static accesses. It is seen that when this scheduling system is implemented in an industry standard FPGA based co-simulator, evaluation fidelity is maintained and significant enhancement in overall functional verification performance is achieved.