Performance modeling based on core/cache design validation results for predictive analysis

The product development phase of a single processor design from inception till production is an extremely long process taking up to ~4 years per cycle. Along the way, numerous tools have been developed for pre-silicon performance prediction in order to forecast the yield, power and frequency of the product. These data are critical in order for product and resource planning to be carried out efficiently. However, with the ever changing market trends, we can rarely predict with great accuracy the desired performance range or feature set which is currently in demand. Therefore, there is a dire need for a systematic and effective method of post-silicon predictive analysis with regards to silicon performance parameters such as power, frequency/level and yield. Prediction based on post-silicon measured data are often more accurate (albeit heuristic) if compared to pre-silicon predictions. With the availability of a post-silicon based performance model, ad-hoc predictive analysis can be carried out for a variety of performance configurations without the need of having to carry out a full scale volume characterization on the silicon.