Architecture and bus-arbitration schemes for HDTV SoC decoder

it is a great challenge to design an On-Chip Bus (OCB) system to meet the extremely high bandwidth requirements in HDTV SoC decoder. In this paper, an OCB system with high throughput and flexibility based on the multi-bus architecture is proposed. A static time division multiplexed scheduling arbitration with central arbitration structure is also brought forth thereafter. Finally, a bus switch with multi-level arbiter structure is constructed. Simulation results show that the OCB system can ensure the real-time performance of the whole decoder very well.