A hybrid high-performance embedded Processing System

In this paper, we analyze the speedup formula, and expand the formula in detail. After discuss the timing problems of parallel computing, we give some designing rules, specially applied to HPEC (high-performance embedded computing) systems. Further analyzing the characteristics of HPEC system, a modular processing architecture is proposed. Due to the development of interconnection technologies, we design a type of hybrid PE (Processing Element) architecture, and describe the compositions of the PE. The implementation methods of the hybrid PE are described. An actual platform is established to certify the feasibility and performance of the system.