An efficient pulse flip-flop based launch-on-shift scan cell

At-speed testing is essential for VLSI ICs implemented in nanometer technologies, operating at high clock speeds. Traditional scan based methodologies can be used for at-speed testing using a transition delay fault model. There are two common techniques to launch the transition-launch-on-shift (LOS) and launch-on-capture (LOC). LOS gives better fault coverage than LOC, but the main drawback of LOS is its requirement of a global at-speed scan enable (SE) signal that needs to be distributed across the IC. In this paper, we propose a pulsed flip-flop based LOS scan cell (PUFLOS cell) and a fast local scan enable generation circuit Our pulsed flip-flop based scan cell has 23.2% lower power dissipation and 27.3% better timing than a conventional muxed D-flip-flop based LOS scan cell. The layout area of our PUFLOS cell is 21% smaller than conventional LOS scan cell. Monte Carlo simulations demonstrate that our design is more robust to process variations than the conventional scan cell.