A rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier

An almost rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier is presented. It is based on a class AB fully differential two stage amplifier. It uses the miller compensation capacitor to hold the output and a duplicate of the output stage to ensure offset cancellation and proper common mode control. Simulation results, in 0.35 μm CMOS technology, show power consumption of 3 mW with ± 1.25 V supplies. The total harmonic distortion, for a differential input of ± 2.4 V_pp at 10 kHz, is less than -56 dB. The error introduced by the rectification is less than -100 dB.