Mapping algorithms for MPSoC synthesis

With ever increasing complexity of modern embedded systems, Multiprocessor Systems on Chip have emerged as a tradeoff solution between traditional general purpose processor or DSP design, and implementation in custom hardware. Such systems are usually comprised out of various processing elements and their synthesis includes various partitioning, mapping and scheduling strategies with goal to optimize multiple constraints. Moreover, shortened time to market and rising software complexity calls for synthesis automation. Transaction Level Model (TLM) has evolved as the next level of abstraction for MPSoC synthesis because it enables high-speed synthesis and adequate accuracy. In this paper, we implemented a group of mapping algorithms for MPSoC synthesis in order to automate the overall design flow. As a case study, we evaluated described algorithms on a MPSoC platform using JPEG encoder application. Design is optimized for performance and results are discussed accordingly.