A shallow-trench-isolation flash memory technology with a source-bias programming method

A flash memory cell with a self-aligned shallow-trench isolation structure and a novel source-bias programming method has been developed. Using a shallow-trench technology to form field isolation between the memory cells results in high-voltage parasitic transistor characteristics and enables the isolation structure to be fabricated at low temperature, which leads to high endurance. By applying a positive bias to the source terminal during programming, the programming speed is maintained even for short-channel-length memory cells with a low drain-source breakdown voltage.