Effect of body-charge on fully- and partially-depleted SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially depleted SOI device design space. Floating-body effects are incorporated into the device design criteria, V/sub T/ and I/sub OFF/ via transient-based evaluation of device performance using calibrated 2-D device simulation. Using this methodology, the worst-case shifts in V/sub T/ and I/sub OFF/ due to hysteretic floating-body charge are quantified for L/sub eff/-0.2 /spl mu/m and 0.1 /spl mu/m design spaces. The effect of reducing effective bulk lifetime in widening the 0.1 /spl mu/m design space is demonstrated.