An optimized ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID reader

A 3rd-order 3-bit single-loop ΔΣ modulator in fractional-N frequency synthesizer for UHF RFID Reader is optimized in terms of phase noise. Feed forward and feedback path structure is proposed in the ΔΣ modulator. The location of zeros and poles are placed at desired frequency for noise shaping by configuring feed forward and feedback coefficients. A fully integrated ΔΣ fractional-N frequency synthesizer with digital ΔΣ modulator is implemented in 0.18μm CMOS technology. The measured phase noise of the proposed ΔΣ fractional-N frequency synthesizer is -76dBc/Hz in-band and -125dBc/Hz at 1MHz offset from 856 MHz carrier and a loop bandwidth of 50 kHz. The rms jitter is 6.74ps and the integrated phase noise is 2.08^o from 10kHz to 10MHz frequency offset.