Loss comparison of two and three-level inverter topologies

This paper investigates semiconductor and DC-link capacitor losses in two two-level and two three-level voltage source inverters. The components of the four inverters are selected to have appropriate voltage and current ratings. Analytical expressions for semiconductor losses are reviewed and expressions for DC link capacitor losses are derived for all topologies. Three-level inverters are found to have lower semiconductor losses, but higher DC-link capacitor losses. Overall, the three-level Neutral-Point-Clamped inverter proved to be the most efficient topology.