Micropipeline DSP-ASIC for a DS-SS receiver

This paper presents a fully asynchronous DSP for a Direct-Sequence Spread Spectrum (DS-SS) radio receiver. Issues relevant to micropipeline VLSI implementation and performance are discussed. The circuit has been designed using a standard cell library in 0.8 /spl mu/m CMOS and contains 100,000 transistors. The receiver handles up to 48 million samples per second and the power consumption is 600 mW.