Pulse shaping and clock data recovery for multi-gigabit standard compliant 60 GHz digital radio

This paper presents the first ultra low power (5 mW) multi-gigabit pulse-shaping filter and clock data recovery circuits fully integrated in a 90-nm CMOS wireless digital radio meeting the specifications of 60 GHz wireless standards. The architecture features a 4.4 Gsps capable 13-tap FIR pulse shaping filter on the TX side, and a dual loop clock data recovery with on-chip loop filter on the RX side to suppress the high frequency jitter introduced by the pulse shaping. Using a fully integrated 60 GHz TDD transceiver embedding the presented solution, a 95% reduction of the high frequency jitter has been measured at the standard nominal 1.728 Gbps data rate. The solution features a minimal power overhead of 5 mW from 1 V voltage supply.