An ultra low voltage amplifier design using forward body bias folded cascode topology for 5GHz application

In this paper a very low-voltage design method for a 5 GHz folded cascade topology amplifier is presented. Comparing to the conventional cascade topology our design has a better performance regarding the amplifier's power dissipation (8 mW for a 0.7 V power supply) and its high gain (20.8 dB). Circuit simulations by the use of H-Spice and a standard TSMC 0.18 um CMOS technology confirmed our design goals. The paper presents the tradeoffs involved in the circuit design and the design for performance issues.