Spin-on dielectric liner TSV for 3D wafer level packaging applications

Imec is developing application specific through silicon vias (TSV) technologies for Si thicknesses of 50 and 100μm in wafer level packaging (WLP) area where thin dies are stacked and electrically connected to each other through post CMOS processed TSVs and (micro-) bumps. 3D-WLP TSV flavors are developed using spin-on dielectric polymers as isolation layer. Electrical results of the TSV-connected daisy chains and the reliability of these TSVs while undergoing thermal cycle tests is also addressed.