FPGA design for multi-filtering techniques using flag-bit and flicker clock

Real time systems typically suffer from delay in data processing. This delay is caused by many reasons such as computational power, processor unit architecture, and synchronization signals in these systems. In order to increase the processing power, a new architecture and clocking technique is carried out in this paper hence the performance. This new architecture design called Embedded Parallel Systolic Filters (EPSF) would process data gathered from sensors and landmarks using a high density FPGA chip. The results show that EPSF architecture and bit-flag with a flicker clock perform significantly better in multiple input sensors signals under both continuous and interrupted conditions. Unlike the usual processing units in previous tracking and navigation systems used in robots, this system allows autonomous control of the robot through multiple techniques of filtering and processing strategy. Furthermore, it also offer a speedy performance that minimizing the delay about 50%.