A 0.6-V delta-sigma ADC with 57-dB dynamic range

In this paper, an ultra-low-power and low-voltage single-loop second-order delta-sigma analog-to-digital converter (ADC) is presented. With the forward-body-bias technique, the threshold voltage of the transistors is effectively reduced, enabling low-voltage circuit operation in a standard CMOS process. In addition, due to the use of bootstrapped switches and a clock booster scheme, the conductance-gap problem is generally prevented for the switched-capacitor circuits. The prototype is fabricated in a 0.18-µW CMOS process for demonstration. Consuming a dc power of 1.5 µW from a 0.6-V supply, the proposed ADC exhibits a dynamic range of 57.5dB and a peak spurious-free dynamic range (SFDR) of 60dB at a clock speed of 800 kHz and an oversampling ratio (OSR) of 64. The chip area of the fabricated circuit is 0.51mm².