RS encoder design based on FPGA

A time-domain RS (Reed-Solomon) encoder was studied in this paper. Firstly analyzed coding theory of RS codes under the finite field, and focuses on the implementations of constant coefficients parallel multiplier under regular basis. On this basis, designed the encoder of RS (255,223) symmetrical structure in the Quartus7.0 build environment using the symmetry of polynomial coefficients, and use Matlab to prepare RS encoder debug and procedures verification, finally, obtained simulation results with the ModelSim5.8. The results show that the encoder is in good condition, and speed and occupancy characteristics of the hardware resources are limited compared with the existing type design.