A high-throughput low-power hardware architecture for H.264 deblocking filter

In this paper we present a high throughput low power hardware architecture of deblocking filter for H.264/AVC. In order to enhance throughput, we propose five-stage pipeline filter core and novel double-filter architecture to process vertical and horizontal edges simultaneously. A novel parallel filtering order is adopted not only to eliminate structure hazard but also to efficiently reuse the intermediate data and reduce SRAM access times. In addition, our architecture utilizes clock gating schemes for both filter cores and transposes to further reduce power consumption. While working at clock frequency of 150MHz, synthesized under 0.13um CMOS standard cell technology, our design achieves the throughput of 1562kMB/s, which could easily meet the throughput requirement of all the levels in H.264/AVC video coding standard and the power consumption of 0.6μW per macroblock which is suitable for mobile applications.