Research and Partial analysis of overhead of a partition model for a Partially Reconfigurable hardware in a data-driven machine - chicflow

Computer applications have become increasingly more complex and require greater processing capacity. In order to achieve higher performance for these applications, algorithms are often implemented in Field-Programmable Gate Arrays (FPGAs). However, most of the Computer-Aided Design (CAD) tools still uses Hardware Description Languages (HDL), which are complex if compared with imperative High Level Languages (HLL). ChipCflow is a tool that aims to convert HLL to HDL, using the dynamic dataflow model and Active Partial Reconfiguration (APR). In this paper we present a research report for the hardware architecture's partition model, necessary for the correct allocation of Dataflow Graphs (DFGs) into FPGA's fabric using APR. In order to calculate system's logic overhead, we show some results which denotes a ratio between the operator's logic and the necessary reconfigurable area, as well as some guidelines about the reconfiguration time of these reconfigurable areas.