A Network on Chip Architecture and Performance Evaluation

Networks-on-chip (NoCs) have emerged as an alternative to ad-hoc wiring or bus-based global interconnection in Systems-on-Chip (SoCs). The architecture of network significantly determines system performance. This paper proposes a network on chip architecture with 2-demention mesh topology, odd-even routing algorithm, wormhole switching technique and only input buffers. The size of packet is 20 bytes and that of flit is 5 bytes. The performance of proposed architecture is evaluated based on metrics of latency and throughput per channel under Constant Bit Rate (CBR) and Bursty traffic. For the proposed architecture, the evaluation results reveal that the average latency of whole network channels is 1.97 cycles under CBR traffic and 1.92 cycles under Bursty traffic. The average throughput of whole network channels is 8.8555 Gbps under CBR traffic and 8.8212 Gbps under Bursty traffic.